CADENCE 2008 NEWS : New Allegro and OrCAD 16.2 Release Helps Companies Deal with the Latest Design Challenges

New Allegro and OrCAD 16.2 Release Helps Companies Deal with the Latest Design Challenges


The Cadence® Allegro® and Cadence OrCAD® family of products for PCB design and IC packaging/SiP design provide automation, advanced co-design, and constraint-driven flows that speed product development—from concept and capture to manufacturing. The latest Allegro and OrCAD release (16.2) enhances these solutions with new capabilities that address current and future business-driven technology challenges, including miniaturization, shorter product lifecycles, increasing design speeds, and environmental concerns.

Press Releases:
New Cadence Design Technology Tackles Miniaturization, Product Design and Low-Power Challenges for IC Package/SiP Designers

Cadence Introduces Constraint-Driven High-Density-Interconnect Design Flow for PCB


Miniaturization/High-Density Interconnect

In the area of product miniaturization, significant improvements for designers using high-density interconnect (HDI) will be of particular value to customers in the high-end consumer and wireless handheld electronics market, as well as in the computing and networking segments where users are seeking a constraint-driven HDI design flow. "Cadence has excelled in constraint-driven PCB design flows for many years, but customers also increasingly demand an HDI capability," explains Steve Kamin, Group Director PCB and IC Packaging Product Marketing, Cadence Design Systems. "With the significant improvements in the latest release of our PCB and IC packaging technology, Cadence now offers both of these capabilities, and some of our customers already are seeing the benefits of our constraint-driven HDI design flow."

"Harris has worked closely with Cadence on improvements in Allegro," said Charlie Davies, Principal ECAE Application Engineer at Harris Government Communications Systems Division. "We are part of a small, diversified group of customers providing feedback to Cadence on improvements in Allegro 16.2. The biggest improvement in the Allegro 16.2 release has been in the area of designing PCBs using a build-up process with High-Density Interconnects. With the addition of capabilities for HDI, Allegro provides an excellent constraint-driven HDI design Flow. These advances along with other ease-of-use improvements will significantly improve our ability to execute our most difficult HDI design challenges, while reducing our design cycle time."

Enhancements such as these make 16.2 a very important release for PCB and IC package designers. For example, the HDI capability includes new features such as enhanced design rules for microvias and same-net elements, along with powerful automation-assisted interconnect and via pattern insertion. Manufacturing IP-driven wirebonding from Kulicke & Soffa and co-planar waveguide modeling further boost productivity and reduce manufacturing-driven ECOs.

Shrinking Product Lifecycles

To deal more effectively with product lifecycle issues, the Allegro and OrCAD 16.2 release delivers features such as extended rule-driven assembly rule checking for IC packages, auto-intelligent step and repeat of complex placement patterns, and enhanced automation for PCB layout-driven RF design. It also enables IC package/SiP team-based design to reduce design cycle time and make resource usage more efficient.

Additionally, all Allegro and OrCAD products—from front-end design creation to signal integrity to back-end layout—have been enhanced in the 16.2 release. One new capability enables customers to integrate RF circuits on PCBs together with digital and analog circuits. The Allegro PCB RF Option achieves this with two major enhancements: a bi-directional interface with the Agilent ADS RF design environment, and a new layout-driven RF design capability that makes it easier to modify RF circuits. The layout-driven RF design capability in the Allegro PCB RF Option also allows users to add RF circuit elements—stripline or microstrip elements—and the system will automatically create RF schematic elements through a back-annotation process. This eliminates the need for RF designers to manually create RF schematics for changes made in the layout, shortening design cycle times and reducing the risk of introducing manual errors.

The proven Cadence constraint-driven PCB design flow also provides additional control of constraints that electrical engineers need in specifying their design intent. Engineers can now specify physical and spacing constraints on critical nets and embed those in the design. These constraints are required for signals such as those found in DDRx memory interfaces, where the engineer needs to specify line widths and spacing to manage impedance and shield critical signals from crosstalk.

Cadence OrCAD Capture further delivers improved capabilities for designing FPGAs into products. Users can easily import an FPGA’s pin assignment from FPGA vendor tools. It also creates split symbols, and allows users to control how the symbols are split. This makes it easier to integrate an FPGA into the PCB design. Should a user choose to make changes to the FPGA pin assignment, OrCAD Capture provides the capability to export an updated pin assignment to the FPGA vendor’s tool. With this release, it supports Altera and Xilinx formats for import and export. Future support for other vendors will be provided based on customer requests.

Users of the 16.2 release will also notice improvements to the Graphical User Interface and Use Models in Allegro PCB Editor as well as other Allegro and OrCAD products. Enhancements include a new application mode for placement in Allegro and OrCAD PCB Editors, improved snapping capabilities with many choices on RMB, and new font support and keyboard shortcuts in Allegro Design Entry HDL.

Increasing Design Speeds/Streaming Data

As video data is being pervasively streamed throughout the Internet and wireless infrastructures, many products now require parallel memory interfaces (i.e. DDR3) running at speeds over a gigahertz and serial interfaces (i.e. PCI Express) transmitting 5 to 10 gigabits per second. The 16.2 release will help accelerate the development of these designs by enabling more accurate simulation and compliance testing of high frequency interfaces. Standard eye masks can now be easily incorporated into multi-bit simulations to insure that bit error rate requirements are met. New high frequency field solver technology is available to create S-parameter models for PCB structures and enhanced 3D field solver technology from preferred technology partner, Apache Design Solutions, can now be incorporated into the IC Package and SiP SI solutions to ensure accurate die to die modeling of high frequency interconnect. Modeling of advanced SerDes transceivers with the newly adopted IBIS-AMI standard now enables simulations with devices from different vendors at opposite ends of the serial link. This release includes a model development kit that can be used to develop IBIS 5.0 AMI compliant models. The new IBIS 5.0 standard is a result of Cadence, SerDes vendors, and other EDA companies coming together to enable accurate simulations of devices that are required for the latest serial link standards.

Environmental Concerns/Green Design

With the increasing awareness of the need to develop products that help protect the Earth’s climate and conserve resources, the 16.2 release helps companies go green. Design teams can make their products more efficient using new capabilities such as IC package power delivery analysis (which includes an integrated power analysis flow that is supported by 3D extraction of signal, power, and ground signals). It also includes the ability to optimize package PDN impedance voltage while minimizing voltage ripple. These and other enhancements also help co-design teams to optimize low-power system designs.

From improved high-speed flows to enhanced ease of use across the range of products, users will find a number of ways that the newest release of the Allegro and OrCAD family of products improves productivity and helps to address today’s and tomorrow’s critical challenges.

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Cadence益華®快板®和Cadence的orcad ®系列產品為PCB設計和IC封裝/ SIP的設計提供了自動化，先進的協同設計，和約束驅動的流動速度，產品開發從概念和捕捉到製造業。

最新Allegro及orcad Capture（ 16.2 ） ，提高這些解決方案與新功能，解決當前和未來的業務驅動的技術挑戰，包括小型化，縮短產品的生命週期，提高設計速度，以及對環境的關注。







新聞發布稿：
新的Cadence設計技術處理的小型化，產品設計及低功耗的挑戰，為IC封裝/ SIP的設計者



Cadence益華介紹了約束驅動的高密度互連設計流量為印刷電路板


小型化/高密度互連

在該地區的產品小型化，顯著改善，為設計師使用的高密度互連（ HDI ）宣布，將具有特殊價值的客戶，在高高端消費類和無線手持電子產品市場，以及在計算和網絡部分用戶尋求約束驅動人類發展指數的設計流程。 “ Cadence的出色，在約束驅動PCB設計流量為多年，但顧客的需求也越來越多的人類發展指數的能力， ”解釋史蒂夫kamin ，集團董事PCB和IC封裝產品營銷， Cadence設計系統。 “與顯著的改善，在最新發布的我國PCB和IC封裝技術， Cadence公司現在提供這兩項功能，和我們的一些客戶已經看到了好處，我們的約束驅動設計流程的人類發展指數” 。



“哈里斯已緊密合作， Cadence公司，就改善中快板，說： ”查理戴維斯，主要ecae應用工程師在哈里斯政府通信系統部。 “我們的一個組成部分，小，多元化的集團客戶提供反饋，以Cadence的改善，在快板16.2 。


最大的改善，在快板16.2釋放已在該地區的設計使用多氯聯苯累積的過程中與高密度互連。加上能力，為人類發展指數，快板提供了一個很好的約束驅動人類發展指數的設計流程，這些進展與其他易於使用的改善將大大提高我們的執行能力，我們最困難的人類發展指數的設計挑戰，同時減少我們的設計週期時間“ 。


改良功能，例如，這些使16.2一個非常重要的釋放PCB和IC封裝設計師。

舉例來說，人類發展指數的能力，包括新功能，如增強的設計規則和相同的微網的要素，隨著強大的自動化輔助互連和威盛格局插入。

製造業的IP驅動wirebonding從庫力索法＆力索法和合作，平面光波導建模進一步提高生產力和降低製造驅動ecos 。



萎縮，產品的生命週期

更有效地處理與產品生命週期的問題， Allegro及orcad 16.2釋放提供的功能，如延長規則驅動的大會規則檢查，為IC封裝，自動智能的一步，並重複複雜的安置模式，提高了自動化PCB佈局驅動的RF設計。它也使IC封裝/ SIP的以團隊為基礎的設計，以減少設計週期時間和使資源使用更有效率。

此外，所有Allegro及orcad的產品從前端設計創造的信號完整性後端佈局-已加強，在2月16日釋放。一個新的能力，使客戶能夠整合射頻電路對多氯聯苯連同數字和模擬電路。

該快板的PCB射頻選項達到這一目標的兩大改進：一bi - directional交與安捷倫廣告RF設計環境，以及一個新的佈局驅動的RF設計的能力，使得更容易修改射頻電路。

佈局驅動的RF設計能力，在快板的PCB射頻選項還允許用戶添加的RF電路元件-帶狀線或微帶要素和系統將自動建立射頻示意圖分子通過回-詮釋的過程。

這無需射頻設計師手動創建的RF!